CVC is a Design Verification (DV) startup firm addressing
various aspects of DV process including (but not limited to):
the Indian market as well as markets abroad (such as AsiaPac,
Eurpoe. Middle-east, Israel).
various aspects of DV process including (but not limited to):
- Verification Methodologies
- Languages for ASIC/FPGA designs
- VIP (Verification Intellectual Property) development
- PIP (Protocol Intellectual Property) development
- Verification auditing
- Resource Augmentation
- Corporate and individual trainings on various Verification
techniques
the Indian market as well as markets abroad (such as AsiaPac,
Eurpoe. Middle-east, Israel).
Markets
CVC's consultancy solution addresses one of the most
challenging and the fastest growing areas in the semiconductor
industry. We focus on Design Verification with advanced
methodologies, tools and languages. Given that functional
verification consumes a large chunk of the design cycle
(anywhere from 50 to 70% and above), we believe our market is
as wide as the entire semiconductor industry!
CVC also actively assist EDA Vendors to validate their new
products, platforms etc. We represent the functional verification
user community as we specialize in this domain. One of the most
challenging tasks for EDA vendors is to find the right team to
test-drive their new products and ideas. End customers prefer
not to suffer from early tool issues. Since our team has the full
exposure to the advanced demands of this industry, we add lot
of value for EDA vendors as flow-testers, specification
reviewers, document writers etc
Technical expertise
CVC’s primary focus is in verification domain. We are experts in
various cutting edge methodologies, tools and languages.
Specifically we have the team with the following expertise areas.
Technologies
CVC's consultancy solution addresses one of the most
challenging and the fastest growing areas in the semiconductor
industry. We focus on Design Verification with advanced
methodologies, tools and languages. Given that functional
verification consumes a large chunk of the design cycle
(anywhere from 50 to 70% and above), we believe our market is
as wide as the entire semiconductor industry!
CVC also actively assist EDA Vendors to validate their new
products, platforms etc. We represent the functional verification
user community as we specialize in this domain. One of the most
challenging tasks for EDA vendors is to find the right team to
test-drive their new products and ideas. End customers prefer
not to suffer from early tool issues. Since our team has the full
exposure to the advanced demands of this industry, we add lot
of value for EDA vendors as flow-testers, specification
reviewers, document writers etc
Technical expertise
CVC’s primary focus is in verification domain. We are experts in
various cutting edge methodologies, tools and languages.
Specifically we have the team with the following expertise areas.
Technologies
- Assertion Based Verification (ABV)
- Constrained Random Verification (CRV)
- Coverage Driven Verification (CDV).
- Verification Methodology for SystemVerilog (VMM)
- Reference Verification Methodology for Vera (RVM)
- Advanced Verification Methodology (AVM)
- SystemVerilog – for Verification, testbench development
(IEEE 1800) - SystemVerilog Assertions
- SystemVerilog for Design
- SystemVerilog Transaction Level Modeling
- Property Specification Language (PSL, IEEE 1850)
- Vera
- E – IEEE 1647
- SystemC – IEEE 1600, SCV
- Verilog, VHDL
- PLI, VHPI etc.
Ajeetha Kumari, M.S
CTO & Managing Director
Ajeetha is the founder of CVC. She has been working in the field
of Design Verification for more than 8 years. She has expertise
in various cutting edge methodologies and languages. She has
worked closely with several EDA vendors and helped them
with their tool evolutions. This list includes both major tool
vendors and many smaller start ups. She has a M.S in Electrical
& Electronics from IIT, Madras (www.iitm.ac.in) and B.E.
from TCE, Madurai. Ajeetha has published articles and tutorials
in various forums such as: DVCon, SNUG, CDNLive! and
various technical articles on online forums. She has co-authored
the following books:
* A Pragmatic Approach to VMM Adoption
* SystemVerilog Assertions Handbook
* Using PSL/SUGAR
CTO & Managing Director
Ajeetha is the founder of CVC. She has been working in the field
of Design Verification for more than 8 years. She has expertise
in various cutting edge methodologies and languages. She has
worked closely with several EDA vendors and helped them
with their tool evolutions. This list includes both major tool
vendors and many smaller start ups. She has a M.S in Electrical
& Electronics from IIT, Madras (www.iitm.ac.in) and B.E.
from TCE, Madurai. Ajeetha has published articles and tutorials
in various forums such as: DVCon, SNUG, CDNLive! and
various technical articles on online forums. She has co-authored
the following books:
* A Pragmatic Approach to VMM Adoption
* SystemVerilog Assertions Handbook
* Using PSL/SUGAR
| Copyright (c) 2008 cvc infotech All Rights Reserved |
CVC Info Tech
Cultivating Ideas
Cultivating Ideas
 |  |  |  |  |  |
| | | | | |
 |
 |