IP Development
Our IP development division focuses on niche IPs for
Verification. Our IPs are usually customized to select customers
and are driven by specific customer demands. Our team has
experience in creating various forms of Verification IPs such as:
PIP - Protocol IP: A set of properties describing the protocol
(such as AXI for instance). These properties are then used as
assertions or assumptions or functional coverage monitors
depending on the nature of device under test. Given CVC's
experience in various assertion languages such as IEEE-1850
PSL and IEEE 1800 SV (SVA), we are the premier supplier of
standalone PIPs in the market. Our team has developed a
specific PIP for a processor bus protocol for a leading ChipSet
company in AsiaPac region.
CIP - Complaince IP: A comprehensive set of functional
coverage model that ensures that your design is tested for 100%
compliance to standard protocols such as PCI. Depending on the
complexity of the protocol, CIPs include a powerful monitor to
extract transaction level information from wire wiggling.
VIP - Verification IP: A full fledged Verification IP that
includes driver (BFM), stimulus generator (including sequences),
monitor, coverage and checkers. Our team has experience in
creating VIPs in various languages such as: SystemVerilog
(IEEE 1800), e (IEEE 1647) and Open Vera.
As it is evident, our perspective of VIPs is quite different from
rest of other IP providers as we work on close interaction with
select customers. Our IP categories are truly driven by popular
demand - many a times our customers have an existing flow and
using a 3rd party VIP doesn't fit their bill easily. This is where
our PIP & CIP come very handy - they can work in existing
flow seamlessly.
Our IP development division focuses on niche IPs for
Verification. Our IPs are usually customized to select customers
and are driven by specific customer demands. Our team has
experience in creating various forms of Verification IPs such as:
PIP - Protocol IP: A set of properties describing the protocol
(such as AXI for instance). These properties are then used as
assertions or assumptions or functional coverage monitors
depending on the nature of device under test. Given CVC's
experience in various assertion languages such as IEEE-1850
PSL and IEEE 1800 SV (SVA), we are the premier supplier of
standalone PIPs in the market. Our team has developed a
specific PIP for a processor bus protocol for a leading ChipSet
company in AsiaPac region.
CIP - Complaince IP: A comprehensive set of functional
coverage model that ensures that your design is tested for 100%
compliance to standard protocols such as PCI. Depending on the
complexity of the protocol, CIPs include a powerful monitor to
extract transaction level information from wire wiggling.
VIP - Verification IP: A full fledged Verification IP that
includes driver (BFM), stimulus generator (including sequences),
monitor, coverage and checkers. Our team has experience in
creating VIPs in various languages such as: SystemVerilog
(IEEE 1800), e (IEEE 1647) and Open Vera.
As it is evident, our perspective of VIPs is quite different from
rest of other IP providers as we work on close interaction with
select customers. Our IP categories are truly driven by popular
demand - many a times our customers have an existing flow and
using a 3rd party VIP doesn't fit their bill easily. This is where
our PIP & CIP come very handy - they can work in existing
flow seamlessly.
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