Publications
We at CVC strongly believe that "Knowledge grows when
shared!". Functional  Verification being an ever growing
challenge, it is only by sharing the unique challenges the
industry can respond to this challenge. CVC takes pride in
participating different conferences and forums  across the
world. CVC has several publications to its credit.  

Books:
Mrs Ajeetha Kumari, our CTO has so far co-authored 3 books in
the area of functional verification all based on cutting edge
technologies/languages:

Papers, tutorials etc.

  • "Pragmatic Adoption of Verification Methodology Manual
    (VMM) for Re-usable Transaction-Based Testbenches in
    SystemVerilog" - Tutorial in DVCon 2007
  • VMMing a  SystemVerilog Testbench by Example- SNUG
    SanJose 2006. This paper received  “Technical Committee
    Award”.
  • “Image processing DSP Verification using SystemVerilog +
    VMM” in SNUG India 2007.
  • Leveraging traditional TB while adopting modern
    Verification technologies" - CDN Live! 2007 at Bangalore
  • Has published the first freely available tutorial on PSL on
        the web.
        http://www.project-veripage.com/psl_tutorial_1.php
           www.synopsys.com/va
  • Presented in various technical conferences in and around     
    Bangalore on varied topics such as:
  • Formal Verification
  • ASIC Verification challenges
  • Industry-Academia gap in VLSI etc.

Online Discussion Forums
TeamCVC actively participate in online forums to share our
views on verification and design issues/problems that general
user community is facing.  Needless to say it is mutually
beneficial as there is lot more to learn for ever. Here are some of
the forums where we are very active:        
http://www.verificationguild.com,                              
http://groups.google.com/group/comp.lang.vhdl ,  
http://groups.google.com/group/comp.lang.verilog ,
http://groups.yahoo.com/group/ASICDESIGN/ ,
http:www.edaboard.com
http:www.ovmworld.org
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